Title:
半導体装置
Document Type and Number:
Japanese Patent JP6990272
Kind Code:
B2
Abstract:
By using a conductive layer including Cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased.
Inventors:
Sanpei Yamazaki
Jun Oyama
Masahiro Takahashi
Hideyuki Kishida
Miyanaga Shoji
Sohei Sugao
Hideki Uochi
Nakamura Yasuo
Jun Oyama
Masahiro Takahashi
Hideyuki Kishida
Miyanaga Shoji
Sohei Sugao
Hideki Uochi
Nakamura Yasuo
Application Number:
JP2020091304A
Publication Date:
January 12, 2022
Filing Date:
May 26, 2020
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H01L29/786; G02F1/1368; G09F9/30; G09F9/35; H01L21/28; H01L21/3205; H01L21/768; H01L21/822; H01L23/532; H01L27/04; H01L27/06; H01L29/423; H01L29/49; H01L51/50
Domestic Patent References:
| JP2007165860A | ||||
| JP10253976A | ||||
| JP2008129314A | ||||
| JP2009175483A | ||||
| JP2009124152A |