Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH05102393
Kind Code:
A
Abstract:

PURPOSE: To increase a noise margin of a high speed logic integrated circuit device, etc., by providing a third wiring for inhibiting to supply power to a fixed potential supply point of a low impedance between first and second signal wirings.

CONSTITUTION: A first signal wiring L1 for transmitting a predetermined inner signal is provided between two basic cells provided in a cell row CG2, and a second signal wiring L2 for transmitting other predetermined inner signal is provided between other basic cell provided in the row CG2 and a basic cell provided in a cell row CG3. A third wiring L2 is provided in a shape including a zone for disposing the wirings L1, L2 in parallel between the wirings L1 and L2. The wiring L3 is not operated as a function of a power source supply passage for supplying an operation power, but connected to a fixed potential supply point PVB. Thus, a coupling capacity between the wirings L1 and L2 is reduced to suppress crosstalk noise.


Inventors:
MASUZAWA KAZUTAKA
NAGAI KENJI
Application Number:
JP25887791A
Publication Date:
April 23, 1993
Filing Date:
October 07, 1991
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
HITACHI LTD
International Classes:
H01L21/768; H01L21/822; H01L23/522; H01L27/04; (IPC1-7): H01L21/90; H01L27/04
Attorney, Agent or Firm:
Ogawa Katsuo