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Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH05299450
Kind Code:
A
Abstract:

PURPOSE: To secure moisture resistance by arranging first resin at the periphery of the under face of a chip part, and arranging second resin smaller in permittivity than it inside the first resin.

CONSTITUTION: First resin 5 is arranged at the periphery of the under face of a chip part 4, which includes a section where a bump electrode 1 is formed, and second resin 6 smaller in permittivity than the first resin 5 is arranged inside the first resin 5 at the under face of a chip part 4. That is, since the first resin 5 for reinforcing the bump electrode 1 exists only at the periphery of the under face of the chip part 4, and the second resin 6 existing at the center of the under face of the chip part 4 is smaller in permittivity than the first resin 5, the influence on the operation of the chip part 4 is small. Hereby, the first resin 5 secures the reliability on the bump electrode 1, and the second resin 6 controls the deterioration of the properties of an arithmetic circuit of the first chip 4 or a signal transmission line 3, whereby the reliability on moisture resistance, etc., can be secured.


Inventors:
YOSHIMASU TOSHIHIKO
Application Number:
JP10490592A
Publication Date:
November 12, 1993
Filing Date:
April 23, 1992
Export Citation:
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Assignee:
SHARP KK
International Classes:
H01L21/56; H01L21/321; H01L21/60; H01L23/12; H01L23/15; H01L23/28; H01L23/29; H01L23/31; (IPC1-7): H01L21/56; H01L21/321; H01L23/12; H01L23/15; H01L23/28; H01L23/29; H01L23/31
Attorney, Agent or Firm:
Shintaro Nogawa



 
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