PURPOSE: To enlarge collector junction capacity, and moreover to reduce the soft error to be generated by α rays at a planar type bipolar RAM integrated circuit by a method wherein at the inside of the circuit, an N type buried layer in the region to form the memory cell part is made to have high concentration, and is made to come in contact with the base region.

CONSTITUTION: Junction capacity between the collector and the base is enlarged by making the base region 5 of the planar N-P-N transistor (Tr) consituting the memory cell part to come in contact with the high concentration N type buried layer 1. While by suppressing impurity concentration of the N type buried layer of the N-P-N Tr constituting the peripheral circuit to low, and making as not to come in contact with the base region, the withstand voltage and the high speed property of the Tr is held, and the rate of margin against the soft error to be generated by α rays is enlarged.