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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS5929456
Kind Code:
A
Abstract:

PURPOSE: To reduce parasitic capacitance largely, and to improve high-frequency characteristics by coating at least the whole side surface of a Schottky metal being in contact with a semiconductor base body with an insulating layer.

CONSTITUTION: An epitaxial layer 102 displaying a conduction type reverse to a semiconductor substrate 103 is grown on the substrate, and a molybdenum layer 105 is formed. The molybdenum layer 105 is processed in a pattern for forming a Schottky barrier, and the whole surface is coated with an oxide film layer 104. One parts of an oxide film layer 109 on the molybdenum layer 105 and an ohmic ion implantation layer 108 are removed, a window for extracting a Schottky electrode and a window for extracting an ohmic electrode are bored, and the metal as the electrodes is evaporated from an upper surface and the Shottky electrode 106 and the ohmic electrode 107 are formed. Accordingly, the parasitic capacitance can be reduced largely because there is no section of which the molybdenum layer 105 and an electrode metallic layer form MOS capacitance together with the semiconductor substrate through the oxide film layers, that is, the structure in which a parasitic element is formed is avoided.


Inventors:
TAKASHINA SATSUJI
Application Number:
JP14027382A
Publication Date:
February 16, 1984
Filing Date:
August 12, 1982
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L29/872; H01L29/417; H01L29/47; (IPC1-7): H01L29/91
Domestic Patent References:
JPS493031A1974-01-11
JPS5119957A1976-02-17
JPS5630701A1981-03-27
JPS50134582A1975-10-24
Attorney, Agent or Firm:
Uchihara Shin