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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS6240752
Kind Code:
A
Abstract:

PURPOSE: To reduce a chip size by extending the inner ends of power leads disposed on a diagonal line of a package to the center of a semiconductor element to enable providing a power terminal adjacently to a peripheral circuit provided at the center of the element.

CONSTITUTION: Leads 31 connected with terminals of a semiconductor element (pads such as power pads Pvcc) are formed of inner leads 311 extended into a package 5 formed by plastic molding and outer leads 312 extended out of the package 5, and the ends of the leads 311 and the terminals of the element are connected by fine metal wirings (bonding wirings) 33. Thus, it is not necessary to wire power wirings connected with a peripheral circuit region 13 from power pads Pvcc, Pvss along cell array regions 11, 12 at all to largely reduce a chip size (specially chip width), thereby preventing the package from increasing to the maximum limit upon increasing of the capacity of a semiconductor element.


Inventors:
SATO KIMIAKI
TAKEMAE YOSHIHIRO
NAKANO MASAO
KODAMA OSAMI
Application Number:
JP17928485A
Publication Date:
February 21, 1987
Filing Date:
August 16, 1985
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H01L23/50; H01L23/495; (IPC1-7): H01L23/48
Attorney, Agent or Firm:
Aoki Akira