Title:
半導体装置、及び電子機器
Document Type and Number:
Japanese Patent JP7358100
Kind Code:
B2
Abstract:
A semiconductor device capable of performing product-sum operation with low power consumption. The semiconductor device includes first and second logic circuits, first to fourth transistors, and first and second holding units. A low power supply potential input terminal of the first logic circuit is electrically connected to the first and third transistors. A low power supply potential input terminal of the second logic circuit is electrically connected to the second and fourth transistors. The potentials of second gates of the first and fourth transistors are held in the first holding unit as potentials corresponding to first data. The potentials of second gates of the second and third transistors are held in the second holding unit. The on/off states of the first to fourth transistors are determined by second data. A difference in signal input/output time between the first and second logic circuits depends on the first data and the second data.
More Like This:
Inventors:
Hajime Kimura
Yoshimoto Kurokawa
Yoshimoto Kurokawa
Application Number:
JP2019132714A
Publication Date:
October 10, 2023
Filing Date:
July 18, 2019
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
G06G7/60; G06N3/063; H01L21/8234; H01L27/088; H01L29/786
Domestic Patent References:
| JP2017228295A | ||||
| JP201553008A | ||||
| JP2017208815A |
Previous Patent: Yogurt and yogurt manufacturing method
Next Patent: Method for oligomerization of butenes by determining the rate of acidic catalysis
Next Patent: Method for oligomerization of butenes by determining the rate of acidic catalysis