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Title:
半導体装置、及び該半導体装置を利用したシステム
Document Type and Number:
Japanese Patent JP6882025
Kind Code:
B2
Abstract:
To provide a semiconductor device which can execute the product-sum operation. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. First analog data is stored in the first memory cell, and reference analog data is stored in the second memory cell. The first memory cell and the second memory cell supply a first current and a second current, respectively, when a reference potential is applied as a selection signal. The offset circuit has a function of supplying a third current corresponding to a differential current between the first current and the second current. In the semiconductor device, the first memory and the second memory supply a fourth current and a fifth current, respectively, when a potential corresponding to second analog data is applied as a selection signal. By subtracting the third current from a differential current between the fourth current and the fifth current, a current that depends on the sum of products of the first analog data and the second analog data is obtained.

Inventors:
Yoshimoto Kurokawa
Application Number:
JP2017051082A
Publication Date:
June 02, 2021
Filing Date:
March 16, 2017
Export Citation:
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Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
G06G7/12
Domestic Patent References:
JP2014194837A
JP7134899A
JP4127467A
JP2004110420A
JP6274661A
JP2007142195A
JP9065032A
JP2012150875A
Foreign References:
WO2015124770A1