Title:
半導体装置及びその製造方法
Document Type and Number:
Japanese Patent JP4271590
Kind Code:
B2
Abstract:
In a semiconductor device, via holes are formed around a chip buried in a package, one end of a conductor filled in the via hole is covered with a pad portion exposed to the outside, and a wiring layer connected to the other end of the conductor is formed. The portion (pad portion) of the wiring layer which correspond to the conductor is exposed from a protective film, or an external connection terminal is bonded to the top of the pad portion. Electrode terminals of the chip are connected to the wiring layer, and the opposite surface of the chip is exposed to the outside.
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Inventors:
Takeharu Noji
Takayanagi Hidenori
Takayanagi Hidenori
Application Number:
JP2004011666A
Publication Date:
June 03, 2009
Filing Date:
January 20, 2004
Export Citation:
Assignee:
Shinko Electric Industry Co., Ltd.
International Classes:
H01L25/10; H01L21/4763; H01L25/18; H01L21/60; H01L21/68; H01L23/48; H01L23/498; H01L23/538; H01L25/11
Domestic Patent References:
| JP2003318323A | ||||
| JP2001110829A | ||||
| JP2002359323A | ||||
| JP2001339011A | ||||
| JP2000021919A |
Attorney, Agent or Firm:
Keizo Okamoto