Title:
半導体装置およびその製造方法
Document Type and Number:
Japanese Patent JP4922753
Kind Code:
B2
Abstract:
A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.
Inventors:
Junko Iwanaga
High Ki Tsuyoshi
Yoshihiko Kanzawa
Karuta Haruyuki
Tetsu Saitoh
Takahiro Kawashima
High Ki Tsuyoshi
Yoshihiko Kanzawa
Karuta Haruyuki
Tetsu Saitoh
Takahiro Kawashima
Application Number:
JP2006507677A
Publication Date:
April 25, 2012
Filing Date:
March 19, 2004
Export Citation:
Assignee:
Panasonic Corporation
International Classes:
H01L27/088; H01L21/336; H01L21/8234; H01L29/423; H01L29/78; H01L29/786
Domestic Patent References:
| JPH06302818A | 1994-10-28 | |||
| JPH1168069A | 1999-03-09 | |||
| JPH05167043A | 1993-07-02 | |||
| JPS6276734A | 1987-04-08 | |||
| JP2002110963A | 2002-04-12 | |||
| JPH05110083A | 1993-04-30 | |||
| JPS63131565A | 1988-06-03 | |||
| JP2002118255A | 2002-04-19 |
Foreign References:
| US4996574A | 1991-02-26 |
Attorney, Agent or Firm:
Hiroshi Maeda
Hiroshi Koyama
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Atsushi Fujita
Kazunari Ninomiya
Tomoo Harada
Iseki Katsumori
Seki Kei
Yasuya Sugiura
Hiroshi Koyama
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Atsushi Fujita
Kazunari Ninomiya
Tomoo Harada
Iseki Katsumori
Seki Kei
Yasuya Sugiura