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Title:
半導体装置およびその製造方法ならびに製造装置
Document Type and Number:
Japanese Patent JP5091532
Kind Code:
B2
Abstract:

To uniformly depress a lead frame 4 to a second insulating layer 3 to sufficiently cure a first insulating layer 2 and the second insulating layer 3 by avoiding an adverse effect on a semiconductor element due to heating for curing the first insulating layer 2 and the second insulating layer 3.

A joint strength between the second insulating layer 3 and the lead frame 4 is increased by forming a hardened first insulating layer 2 on a heatsink 1, forming a half-cured second insulating layer 3 with its hardness lower than that of the first insulating layer 2 on the first insulating layer 2, and depressing the lead frame 4 to the second insulating layer 3 and thermosetting the second insulating layer 3. Semiconductor elements 5a, 5b, 5c, 5d, 5e, 5f are mounted on the lead frame 4, and the semiconductor elements 5a, 5b, 5c, 5d, 5e, 5f are sealed by a resin 7 for sealing so that the lower surface of the heatsink 1 and a part of the lead frame 4 are exposed.

COPYRIGHT: (C)2009,JPO&INPIT


Inventors:
Hayasaka power
Akifumi Yokomizo
Hideaki Baba
Application Number:
JP2007106621A
Publication Date:
December 05, 2012
Filing Date:
April 15, 2007
Export Citation:
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Assignee:
Nippon Inter Co., Ltd.
International Classes:
H01L23/34; H01L23/36; H01L23/48; H01L25/07; H01L25/18
Domestic Patent References:
JP2002076204A
JP2000031338A
JP2000058575A
JP3008445U
Attorney, Agent or Firm:
Kozo Sakakibara



 
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