Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS PHASE TESTING METHOD
Document Type and Number:
Japanese Patent JP3934283
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To conduct effectively a phase margin test of a plurality of clocks by arranging a phase testing circuit in a system LSI requiring a plurality of clocks.
SOLUTION: In a testing method of phase between input clocks of a semiconductor integrated circuit device (system LSI) needing a plurality of clocks, arbitrary clocks, e.g. a CLOCK1 and a CLOCK2 are selected out of a plurality of clocks, CLOCK1-CLOCKN. Inverted data Q bar which are transferred from a flip-flop 2 are selected by using the selected clocks, and held as time series data by using a timing check circuit 400. By comparing the time series data with expectation data, phase check is collectively performed regarding the selected clocks.
Inventors:
Masaru Sugimoto
Application Number:
JP20253299A
Publication Date:
June 20, 2007
Filing Date:
July 16, 1999
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
G01R31/28; G01R31/319; G06F11/30; H01L21/822; H01L27/04; (IPC1-7): G01R31/28; G01R31/319; H01L27/04; H01L21/822
Domestic Patent References:
| JP200046919A |
Attorney, Agent or Firm:
Hiroaki Sakai