Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE USING NEURAL NETWORK
Document Type and Number:
Japanese Patent JP2624143
Kind Code:
B2
Abstract:
PURPOSE: To reduce the number of components by performing pulse density modulation and pulse width modulation processing inside a neuron and a synapse cell based on an idea in the manner of an analog circuit.
CONSTITUTION: The synapse load value data of 4 bits are inputted and set from a 4-bit memory & counter 21 to two pulse width modulation circuits 22 independent in the direction of arithmetic, the respective inputted pulse widths are modulated by the pulse width modulation circuits 22 corresponding to the respectively set synapse load value data, the pulse width modulated signal of an output 18 of the Ni neuron cell is sent to the input pulse of the Nj neuron cell, and the pulse width modulated signal of an output 19 of the Nj enuron cell is sent to an input bus 23 of the Ni neuron cell. The input paths of Ni and Nj neuron cells are respectively composed of an excited path and a suppressed path and when the synapse load value data are positive, they are sent to the excited path but when those data are negative, they are sent to the suppressed path.
Inventors:
Hiroshi Hirabayashi
Application Number:
JP23708093A
Publication Date:
June 25, 1997
Filing Date:
September 24, 1993
Export Citation:
Assignee:
NEC
International Classes:
G06G7/60; G06F15/18; G06N3/063; H01L29/66; (IPC1-7): G06F15/18; G06G7/60; H01L29/66
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)