Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JP3151298
Kind Code:
B2
Abstract:
PURPOSE: To acquire a larger quantity of information with a cell having same area.
CONSTITUTION: Gate electrode G of a transistor Q for memory cell is connected with a word line W while a drain electrode D is connected with a bit line B and a source electrode S is connected with any one of a plurality of voltage signal lines V1, V2,...Vn having different potentials.
Inventors:
Yukimitsu Nagakawa
Application Number:
JP20525492A
Publication Date:
April 03, 2001
Filing Date:
July 31, 1992
Export Citation:
Assignee:
Kawasaki Steel Co., Ltd.
International Classes:
G11C16/04; H01L21/8246; H01L27/112; (IPC1-7): H01L21/8246; G11C16/04; H01L27/112
Domestic Patent References:
| JP63231797A | ||||
| JP6204423A |
Attorney, Agent or Firm:
Toshihiko Kanayama (2 outside)