Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JP3246807
Kind Code:
B2
Abstract:
PURPOSE: To improve a surge-voltage protecting property by causing a current path to be formed through an impurity region in a second well, a buried layer, the other terminal in a first well, and an input terminal when surge voltage is applied to the input terminal.
CONSTITUTION: An npn bipolar transistor Q2 is formed with an n+ type buried layer 12 as a collector, a p type well 16 as a base, and a drain region 25 as an emitter. There is a resistor R2 between an emitter of a bipolar transistor Q1 and the collector of the bipolar transistor Q2 and a base resistor of the transistor Q2 is R1. By causing these transistors Q1 and Q2 to be newly formed, a surge current path is formed which starts from a ground terminal and goes to an input terminal 101 through a source region 27 of the transistor Q1, the n+ type buried layer 12, the drain region 25 of the transistor Q2.
Inventors:
Shigeto Minakami
Application Number:
JP16805393A
Publication Date:
January 15, 2002
Filing Date:
July 07, 1993
Export Citation:
Assignee:
Toshiba Corporation
Toshiba Microelectronics Corporation
Toshiba Microelectronics Corporation
International Classes:
H01L21/822; H01L21/8238; H01L27/02; H01L27/092; H01L29/78; H02H7/20; H01L27/04; (IPC1-7): H01L21/8238; H01L21/822; H01L27/04; H01L27/092; H01L29/78; H02H7/20
Domestic Patent References:
| JP360066A | ||||
| JP61190973A |
Attorney, Agent or Firm:
Kazuo Sato (3 others)
Previous Patent: ファン付きウェアの服本体及びファン付きウェア
Next Patent: FISHWAY CORRESPONDING TO VARIATION OF WATER LEVEL
Next Patent: FISHWAY CORRESPONDING TO VARIATION OF WATER LEVEL