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Patent Searching and Data


Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPH02297970
Kind Code:
A
Abstract:

PURPOSE: To improve data-retaining properties by making thinner a gate insulating film between a floating gate and a control gate and a gate insulating film at a charge-accumulating part of MNOS type constituting EPROMs when constituting and IC with an EPROM and a MNOS type EPROM.

CONSTITUTION: An involatile EPROM consists of a FETQEM where a control gate is provided on a floating gate through a gate insulating film. Also, an EEPROM consists of a FETQFM where a floating gate is provided on a tunnel insulating film and a MISFETQFS for selecting memory for driving it. Further, an EPROM consists of a FETQMM where a gate electrode is provided on a gate insulating film with a charge-accumulating part and a MISFETQMS for selecting memory cell for driving it. Thus, when constituting as in the above, a first gate insulating film 101 is formed by allowing a substrate 1 to be subjected to thermal oxidation and a second gate insulating film 104 consists of a mixed film where SiO2, Si3N4, and SiO2 are laminated in sequence from the lower layer.


Inventors:
KURODA KENICHI
Application Number:
JP11747789A
Publication Date:
December 10, 1990
Filing Date:
May 12, 1989
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H01L21/8247; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): H01L27/115; H01L29/788; H01L29/792
Attorney, Agent or Firm:
Akita Haruki