Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPH033421
Kind Code:
A
Abstract:

PURPOSE: To attain low power consumption in a PLL(Phase Locked Loop) circuit and to miniaturize the whole of a receiver by providing a local oscillation circuit to balance-output an oscillation signal, the PLL circuit with a constant current operation to receive a local oscillation signal as differential input, and a mixer to receive the local oscillation signal with balance input in the same chip.

CONSTITUTION: The local oscillation signal to a PLL circuit block and the mixer 3 is set as the differential input, and the mixer 3, the local oscillation circuit 4, an I/F signal amplifier circuit 5, PLL circuit blocks 6-8 are provided on the same semiconductor substrate. In other words, effective input amplitude can be doubled by forming a programmable counter in symmetrical circuit configuration and setting the local oscillation signal as the differential input, and the loss of a signal can be reduced by providing the components in the same chip, and the normal operation of the programmable counter 6 can be performed even when the amplitude of the local oscillation signal is reduced. In such a way, a small reception circuit device having the PLL circuit block with low power consumption and a wide input band area can be obtained.


Inventors:
WASHIO KATSUYOSHI
OKABE TAKEAKI
TANAKA SATOSHI
NORISUE KATSUHIRO
Application Number:
JP13603789A
Publication Date:
January 09, 1991
Filing Date:
May 31, 1989
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
HITACHI LTD
HITACHI VLSI ENG
International Classes:
H01L21/761; H01L21/76; H01L21/8222; H01L21/8226; H01L27/082; H03D7/00; H03L7/18; H03L7/22; (IPC1-7): H01L21/76; H01L27/082; H03D7/00; H03L7/18; H03L7/22
Attorney, Agent or Firm:
Katsuo Ogawa (1 person outside)



 
Next Patent: JPH033422