To prevent a circuit device from being large in circuit scale and to perform efficient scanning and shifting operation for data by specifying the relation among the number of bits of a shift circuit, the number of a scanning circuit, and the width of a data bus.
Data in a register file 101 are transferred to an N-bit shift circuit 103 and an N-bit scanning circuit 104 through data buses 105 and 106 with M-bit data bus width and the data are shifted in operation units of N bits. Since M bits of the data size of a mathematical operation circuit 102 and N bits of the scan circuit 104 and shift circuit 103 are so related that M=i+N (where (i) is an integer larger than 1, M is an integer larger than 3, and N is an integer larger than 2), data transfer is performed up to (M/N) times or (M/N+1) times to perform M-bit data processing. Therefore, even when the bit size of the data processing increases, an optimum circuit can be constituted in consideration of the circuit scale, chip cost, etc.
KUBOTA SATORU
OGUCHI YASUHIRO
