Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS5877245
Kind Code:
A
Abstract:
PURPOSE:To remove a limit on the connecting position of wirings, and moreover to reduce capacity of the wirings on an unused element of a semiconductor integrated circuit device by a method wherein unevenness of the surface of a first insulating film covering the main face of an Si substrate on the side provided with circuit elements of the plural number is compensated with a second insulating film provided thereon. CONSTITUTION:FET's 204, 205 are formed being separated by a field oxide film 206 on a substrate 200, and the places other than a source and a drain 203 and the connecting parts of a first layer metal wiring 207 are covered with PSG 208, and are covered with insulating polyimide films 209 in succession to flatten the upper part of an unused element 205. Therefore disconnection according to a step part is not generated, and a prohibition about the connecting position of the wirings 207, 211 is cancel on the unused element 205. When the connection prohibiting place is canceled by this way, the degree of integration can be enhanced, and moreover the distances between the metal wirings 207, 211 and the substrate 200 are enlarged by interposition of the insulating film 209 to reduce parasitic capacity. Accordingly the speed of a logic gate is increased.
Inventors:
NISHIO YOUJI
NAKAJIMA KEISUKE
HAMADA NAGAHARU
KUBOKI SHIGEO
IKEDA TAKAHIDE
NAKAJIMA KEISUKE
HAMADA NAGAHARU
KUBOKI SHIGEO
IKEDA TAKAHIDE
Application Number:
JP17461981A
Publication Date:
May 10, 1983
Filing Date:
November 02, 1981
Export Citation:
Assignee:
HITACHI LTD
International Classes:
H01L21/822; H01L21/768; H01L21/82; H01L21/8234; H01L23/522; H01L27/04; H01L27/118; (IPC1-7): H01L21/88; H01L21/90; H01L27/04
Attorney, Agent or Firm:
Katsuo Ogawa (2 outside)