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Patent Searching and Data


Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS6246551
Kind Code:
A
Abstract:

PURPOSE: To minimize wiring-caused parasitic capacity by rendering an interlayer insulating film thicker than a MIM capacitor insulating film and thereby to increase the capacity per unit area of the MIM capacitor by a method wherein the interlayer insulating film has a two-layer laminate in structure and the MIM capacitor insulating film is built of one of the two layers only.

CONSTITUTION: Si ions are implanted into a semi-insulating GaAs substrate 4 for the formation of an implanted layer 5. A lower electrode wiring layer 6 to constitute a lower electrode of a MIM capacitor and metals for an FET and a resistance element are built of AuGe/Ni/Au. Further, the gas electrode 7 of the FET is built of Ti/Al. At this stageof the manufacturing system, insulating films are formed. First, a 5,000-thick SiO2 film is formed by CVD to be a first layer insulating film A11, the SiO2 film is then removed from the region for the MIM capacitor, and then a 3,000-thick Si3O4 film is formed by plasma CVD to be a second layer insulating film B12. Thereafter, an upper electrode wiring layer 9 containing the upper electrode of the MIM capacitor is built of Ti/Au.


Inventors:
NISHIUMA MASAHIRO
OGIO MASAHIRO
KAZUMURA MASARU
Application Number:
JP18568285A
Publication Date:
February 28, 1987
Filing Date:
August 26, 1985
Export Citation:
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Assignee:
MATSUSHITA ELECTRONICS CORP
International Classes:
H01L27/04; H01L21/822; H01L27/01; H01L29/92; H01L49/02; (IPC1-7): H01L27/01; H01L27/04; H01L49/02
Attorney, Agent or Firm:
Koji Hoshino