PURPOSE: To improve the wiring process efficiency of layout, and make the perfect automating of wiring possible, by making the number of wiring channels in the wiring channel region of each cell array differ in accordance with each channel region.

CONSTITUTION: In a semiconductor integrated circuit of gate array system, the following two regions are perfectly separated; cell regions 12W14 in which a group of cell transistors constituting logic is regularly arranged in one- dimensional direction, and wiring regions 15 and 16 in which wirings between each cell 11 are arranged. The respective numbers of wiring channels 17 and 18 in the wiring channel regions 15 and 16 are made different from each other. Thereby, even if arrangement and wiring are made from the central part of a chip, and the wiring is crowded there, the number of the wiring channels of the wiring channel region in the central part of a chip can be made larger than that of the regions excepting the central part. Thus the wiring efficiency can be improved, and automatic layout is enabled.