Title:
半導体集積回路装置
Document Type and Number:
Japanese Patent JP4023598
Kind Code:
B2
Abstract:
A semiconductor integrated circuit device having a test clock generating circuit enabling a high performance test operation and a method of designing a semiconductor integrated circuit device enabling setting of high precision timing margins is disclosed. A test clock generating circuit having a register sequential circuit and a clock output control circuit is provided between a pulse generating circuit and a logic circuit. When a test operation is active, transfer of a clock pulse generated in the pulse generating circuit to the logic circuit is stopped and a test clock pulse operating the logic circuit is outputted using a pulse signal generated in the pulse generating circuit by controlling a clock transfer control circuit with the sequential circuit depending on setting information of a register. The test clock generating circuit is comprised using a logic design tool utilizing a computer in order to test logic circuit functions and timing margins.
Inventors:
Toshikazu Date
Toyoto Ikeya
Masatoshi Kawashima
Toyoto Ikeya
Masatoshi Kawashima
Application Number:
JP2002285006A
Publication Date:
December 19, 2007
Filing Date:
September 30, 2002
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
G01R31/28; G01R31/3183; G01R31/319; G06F11/22; H01L21/82; H01L21/822; H01L27/04
Domestic Patent References:
| JP61042933A | ||||
| JP62159512A | ||||
| JP2002196046A | ||||
| JP7084011A | ||||
| JP11142478A | ||||
| JP2848619B2 | ||||
| JP10267997A | ||||
| JP3328160B2 |
Attorney, Agent or Firm:
Mitsumasa Tokuwaka