Title:
半導体集積回路装置
Document Type and Number:
Japanese Patent JP4205396
Kind Code:
B2
Abstract:
In a semiconductor integrated circuit device, a command decoder is adapted to receive not only an external command but also an internal command. An ECC controller has a command generator and an address generator. When the command decoder decodes an external entry command, the command generator instructs encoding to an ECC-CODEC circuit and the address generator sequentially produces addresses which are supplied to a memory array. The ECC-CODEC circuit produces check bits for error detection/correction with reference to information data of the memory array. Upon completion of an encoding operation of writing the check bits into a predetermined region of the memory array, the ECC controller delivers an end signal to the command decoder as the internal command to make a super self-refresh control circuit start a super self-refresh operation.
Inventors:
Yutaka Ito
Takayuki Aisu
Suzuki Hideyuki
Takayuki Aisu
Suzuki Hideyuki
Application Number:
JP2002315319A
Publication Date:
January 07, 2009
Filing Date:
October 30, 2002
Export Citation:
Assignee:
Elpida Memory Co., Ltd.
International Classes:
G06F12/16; G11C11/403; G11C7/02; G11C11/406; G11C7/10; G11C11/401; G11C29/42
Domestic Patent References:
| JP200368076A | ||||
| JP200256671A |
Attorney, Agent or Firm:
Kenho Ikeda
Shuichi Fukuda
Takashi Sasaki
Shuichi Fukuda
Takashi Sasaki
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