Title:
半導体集積回路装置
Document Type and Number:
Japanese Patent JP5201148
Kind Code:
B2
Abstract:
A semiconductor integrated circuit device includes plural circuit units each having plural logic circuits; and plural power terminals supplying power source from outside to the semiconductor integrated circuit device, in which the plural circuit units each having plural logic circuits have common packaging design with each other, and lengths in a vertical direction and a lateral direction of the circuit units each having plural logic circuits are equal to an even multiple of a distance between the power terminals adjacent to each other.
Inventors:
Yasui
Application Number:
JP2009536881A
Publication Date:
June 05, 2013
Filing Date:
October 09, 2007
Export Citation:
Assignee:
富士通株式会社
International Classes:
H01L21/822; H01L21/3205; H01L21/768; H01L21/82; H01L21/8242; H01L23/522; H01L25/04; H01L25/18; H01L27/04; H01L27/10; H01L27/108
Domestic Patent References:
| JP2003264256A | 2003-09-19 | |||
| JPH10173057A | 1998-06-26 | |||
| JPH05152302A | 1993-06-18 | |||
| JPH0722510A | 1995-01-24 | |||
| JPH0964191A | 1997-03-07 | |||
| JP2003264256A | 2003-09-19 | |||
| JPH10173057A | 1998-06-26 | |||
| JPH05152302A | 1993-06-18 |
Foreign References:
| WO2007099579A1 | 2007-09-07 |
Attorney, Agent or Firm:
Tadahiko Ito