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Title:
SEMICONDUCTOR INTEGRATED CIRCUIT AND IC CARD
Document Type and Number:
Japanese Patent JP2003330555
Kind Code:
A
Abstract:

To provide an LSI for an IC card comprising a stabilized power supply circuit capable of suppressing an excessive inflow current in turning on a power supply, and suppressing the excessive fluctuation of an output voltage VDD1 even if a load of an external power supply or an internal circuit fluctuates rapidly.

The stabilized power supply circuit 100 comprises an output control MOS QO4 to generate an internal power supply VDD1 by inputting the external power supply VDD, and an error amplifier 11 to control a gate of the output control MOS QO4 by comparing a feedback voltage Vret reflecting the internal power supply and a reference voltage Vref. Further, the circuit 100 is provided with a current limiting MOS QD3 connected to a path where the quantity of current is limited, a switch SW2 to connect the current limiting MOS QD3 with the output control MOS QO4 in current mirror connection, and a time constant circuit to turn the switch on for a certain period from turning on the power supply. A voltage clamp means is provided at an output node of the feedback voltage Vret to block that the feedback voltage fluctuates over a certain voltage range.


Inventors:
KADOKAWA SHIGERU
MATSUMURA SATORU
Application Number:
JP2002138349A
Publication Date:
November 21, 2003
Filing Date:
May 14, 2002
Export Citation:
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Assignee:
RENESAS TECH CORP
HITACHI ULSI SYS CO LTD
International Classes:
B42D15/10; G05F3/26; G06F1/26; G06K19/07; H03K17/08; H03K17/16; H03K19/00; (IPC1-7): G05F3/26; B42D15/10; G06F1/26; G06K19/07; H03K17/08; H03K17/16; H03K19/00
Attorney, Agent or Firm:
Tomio Ohinata



 
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