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Title:
SEMICONDUCTOR INTEGRATED CIRCUIT AND ITS TEST METHOD
Document Type and Number:
Japanese Patent JP2004253031
Kind Code:
A
Abstract:

To provide a semiconductor integrated circuit in which threshold voltage measurement of a nonvolatile memory cell can be conducted by linearly changing a word line selection level without directly driving a word line by a D/A converting circuit.

A nonvolatile memory (4), in which stored information is rewritable, is provided with drivers (33R1 to 33Rn) which drive word lines by reading operations and a first power supply circuit (39A) which supplies operating power to the drivers. In a test mode, the operating power supply voltages of the drivers generated by the circuit (39A) are controlled based on the conversion output voltage of the D/A converting circuit. When the threshold voltage of the nonvolatile memory cell is detected for device defect, it is possible to linearly change the operating power supply voltages of the drivers generated by the circuit (39A) in an approximate manner based on the conversion output voltage of the D/A converting circuit. Thus, no current driving capability is required to drive word line loads for the D/A converting circuit.


Inventors:
SEGAWA TOMOKI
Application Number:
JP2003040530A
Publication Date:
September 09, 2004
Filing Date:
February 19, 2003
Export Citation:
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Assignee:
RENESAS TECH CORP
RENESAS NTHN JP SEMICONDUCTOR
International Classes:
G01R31/316; G06F15/78; G11C16/02; G11C16/06; G11C29/00; G11C29/02; G11C29/12; H01L21/822; G01R31/28; H01L27/04; (IPC1-7): G11C29/00; G01R31/28; G01R31/316; G06F15/78; G11C16/02; G11C16/06; H01L21/822; H01L27/04
Attorney, Agent or Firm:
Shizuyo Tamamura