SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME

Title:

SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME

Document Type and Number:

Japanese Patent JP2004327702

Kind Code:

A

Abstract:

To form a self-alignment contact in a self-alignment manner to a gate electrode by forming a silicide on the gate electrode consisting of polysilicon and thereafter forming a silicon nitride film on the gate electrode.

A conductor film 25 and a cap insulation film 27 are formed in order. A laminated film consisting of the cap insulation film and the conductor film is patterned to form the gate electrode 25 consisting of the conductor film. Diffusion areas 29, 30 and 31 which become a source and drain is formed. The silicon nitride film 28 is formed on the side wall of a laminated film. A full-surface silicon nitride film 33 is formed, and a silicon oxide film 34 is deposited. With the silicon nitride film 34 left between gate electrodes, the silicon nitride film 33 on the laminated film is separated, and the cap insulation film 27 left on the top of the gate electrode is removed. On the surface of the gate electrode 25, a metal silicide film 36 is formed, and the silicon nitride film 37 is left on the gate electrode 25.

Inventors:

AOCHI HIDEAKI

Application Number:

JP2003120098A

Publication Date:

November 18, 2004

Filing Date:

April 24, 2003

Export Citation:

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Assignee:

TOSHIBA CORP

International Classes:

H01L21/8238; H01L21/8242; H01L27/092; H01L27/108; H01L29/72; H01L29/76; (IPC1-7): H01L21/8242; H01L21/8238; H01L27/092; H01L27/108

Attorney, Agent or Firm:

Takehiko Suzue
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Sadao Muramatsu
Ryo Hashimoto

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