To provide a semiconductor integrated circuit that can prevent the flow of a through-current from a 1st power supply to ground in a process of rising a 2nd power supply when the 1st power supply of a two-power supply integrated circuit and an input level are determined.

The semiconductor integrated circuit is provided with a control logic section 32 of a VCC1 system that generates a couple of complementary signals GB, GBB corresponding to an input of a control signal, an input section 31 of a VCC2 system receiving an input signal of an input port, a level shift section 10 that outputs a logic signal of the VCC1 system in response to a signal N1 of the VCC2 system from the input section, and a tri-state buffer circuit 34 that is controlled by the signals GB, GBB from the control logic section and the output of which is controlled at a logic level corresponding to a logic signal outputted from the level shift section or a high impedance state. The level shift section has an element that prevents a through-current from flowing from the VCC1 to a ground node in a process of rising the VCC2 when the level of the VCC1 and the input signal is determined.