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Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP2006295359
Kind Code:
A
Abstract:

To adopt a comparatively simple circuit configuration that reduces a relative error of a plurality of DACs and/or a plurality of ADCs used in a wireless LAN communication circuit.

A semiconductor integrated circuit is provided with: a first group of correction circuits for correcting transmission data outputted from an encoder; a plurality of the DACs that convert corrected transmission data into an analog transmission signal and convert a digital reference signal into an analog reference signal in a DAC test mode; a plurality of ADCs including one ADC that converts an analog received signal into received data, converts the analog reference signal outputted from one DAC in an ADC test mode into a plurality of digital signals, and sequentially converts the analog reference signal outputted from a plurality of the DACs in the DAC test mode into a digital signal; and a second group of correction circuits for correcting the received data outputted from the ADCs to output the result to a decoder.


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Inventors:
HIUGA TSUTAE
Application Number:
JP2005110544A
Publication Date:
October 26, 2006
Filing Date:
April 07, 2005
Export Citation:
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Assignee:
SEIKO EPSON CORP
International Classes:
H03M1/12; H04L25/03; H04L27/20; H04L27/36
Attorney, Agent or Firm:
Mutsumi Yanase
Masaaki Utsunomiya
Atsushi Watanabe