Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP3055487
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a pattern layout structure for detecting the internal logic state of a MOS LSI without any contact by irradiating with laser beams from the backside of the LSI.
SOLUTION: Impurity regions 6 are provided at the certain region of a substrate, for example, a wiring channel region 5 between cell group regions 4 of a semiconductor integrated circuit with a logic circuit that is constituted of a CMOS structure on a semiconductor substrate and are connected to the output part of a test target circuit by pattern wiring. The impurity regions 6 are electrically independent of a power supply voltage clamping region and a semiconductor device formation region for constituting an electrical circuit and used to apply laser beams from the backside of a substrate 1.
Inventors:
Masaru Sanada
Application Number:
JP4400497A
Publication Date:
June 26, 2000
Filing Date:
February 27, 1997
Export Citation:
Assignee:
NEC
International Classes:
G01R31/28; H01L21/66; H01L21/82; H01L21/822; H01L23/544; H01L27/04; H01L27/092; G01R31/302; (IPC1-7): H01L27/04; G01R31/28; G01R31/302; H01L21/66; H01L21/82; H01L21/822
Domestic Patent References:
| JP5326717A |
Attorney, Agent or Firm:
Nobuyuki Kaneda (2 others)