Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP3709246
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To supply a large control signal and realize a low voltage loss even when a potential difference between a power source terminal and an output node becomes small by connecting a reference electrode of a driving transistor in a buffer circuit with the power supply terminal.
SOLUTION: This semiconductor integrated circuit includes a differential amplifier, which is mainly constituted by differential transistors Q1 and Q2 and a current source transistor Q9, and further includes a buffer circuit constituted by a driving transistor 10, an operation control transistor Q12, and a control transistor Q11. Herein, by connecting a reference electrode of the driving transistor 10 with a power source terminal VDD, a relatively large control signal can be applied to an output node N2 even when a potential difference between the power source terminal VDD and the output node N2 becomes small. Thus, the buffer circuit functions as a low voltage loss circuit. Further, a gate voltage of the transistor Q10 can be lowered to a grounded voltage, resulting in an enhanced driving ability.
Inventors:
Hitoshi Tanaka
Masakazu Aoki
Kiyoshi Ito
Masakazu Aoki
Kiyoshi Ito
Application Number:
JP22478996A
Publication Date:
October 26, 2005
Filing Date:
August 27, 1996
Export Citation:
Assignee:
株式会社日立製作所
株式会社日立超エル・エス・アイ・システムズ
株式会社日立超エル・エス・アイ・システムズ
International Classes:
G11C11/419; G05F1/56; G11C5/14; G11C11/407; G11C11/409; G11C11/413; H01L21/8242; H01L27/108; H03K5/02; H03K19/00; H03K19/0944; (IPC1-7): G11C11/407; G05F1/56; G11C11/413
Domestic Patent References:
| JP7037381A | ||||
| JP6325568A | ||||
| JP10161758A | ||||
| JP200075941A |
Attorney, Agent or Firm:
Yasuo Sakuta
Katsuo Ogawa
Katsuo Ogawa
Previous Patent: DATUM PLANE SETTING DEVICE
Next Patent: INSTALLING STRUCTURE AND METHOD FOR GREENHOUSE ROOF OR THE LIKE
Next Patent: INSTALLING STRUCTURE AND METHOD FOR GREENHOUSE ROOF OR THE LIKE