PURPOSE: To enable the design of a semiconductor integrated circuit of a synchronous circuit system through an automatic arrangement wiring system and to make clock signals small in transmission delay difference by a method wherein a clock signal wiring is wired inside logic cells traversing cell rows and a buffer cell is provided to the end of each cell row to enhance clock signal drive capacity.

CONSTITUTION: A buffer cell 2 is provided to the ends of cell rows respectively to improve clock signals 1 and 3 in drive capacity, and clock signal wirings 1 and 3 are provided inside logic cells traversing the cell rows. Therefore, the clock signals from the clock signal wirings 1 and 3 are enhanced in drive capacity through the buffer cells 2 and transmitted to the clock signal wirings 1 and 3 which traverse the inside of the logic cells, and the clock input signal of each logic cell is transmitted. By this setup, even if a synchronous circuit is laid out through an automatic arrangement wiring system, the transmission of a clock signal to sections can be restrained from becoming large in delay difference.