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Patent Searching and Data


Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH0645472
Kind Code:
A
Abstract:

PURPOSE: To provide a semiconductor integrated circuit that is expected to reduce the parasitic capacitance of a transmission line and to improve an operating frequency.

CONSTITUTION: In a semiconductor integrated circuit having two parallel transmission lines 3 and 4 installed in a semiconductor substrate, both ends of the signal transmission line 3 are connected between an output circuit 1 and an input circuit 6. Further, the transmission line 4 is installed in parallel with the transmission line 3, and furthermore one end of the transmission line 4 is connected to an output circuit 2 which is signal-wise branched from an output circuit 1, and the other end thereof is opened. A resistance layer 5 is installed so as to have surface overlapping with the transmission lines 3 and 4. Since the transmission line 4 that is in parallel with the transmission line 3 is connected to an output circuit which is branched from the output having the same signal component as that of the transmission line 4, the suspended capapacity that is generated in the signal transmission line can be reduced. As a result, the operating frequency can be improved.


Inventors:
YAKUWA NAOKI
Application Number:
JP19573792A
Publication Date:
February 18, 1994
Filing Date:
July 23, 1992
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L23/12; (IPC1-7): H01L23/12
Attorney, Agent or Firm:
Yoshiyuki Iwasa