PURPOSE: To implement space saving, low power consumption and high reliability, by providing an interface circuit, which selectively controls the input and output of signals between a CPU-IC and a plurality of chips, in a composite chip.

CONSTITUTION: When a CPU-IC 1 inputs data into addresses in a DMAC function chip 6, the IC 1 outputs address signals through terminals AD0∼AU7. At this time an address latching circuit 2 latches the address signals and outputs the signals to a decoding circuit 5 and address inputs A0∼A3 of chips 6∼8. The chip 6 is selected with the decode output, and the specified addresses are selected. Then the data are outputted through the AD0∼AD7 of the IC 1. The circuit 2 is disabled. The data are transferred to D0∼D7 of the chips through an address-data separating/swapping circuit 3. As a result, the data from the IC 1 are transferred to the specified memory region of the chip 6. The data are transferred to the specified memory regions of the other chips 7 and 8 by the same way.