PURPOSE: To reduce the element isolation interval between a P-channel transistor and an N-channel transistor and to make possible an increase in integration by a method wherein one of the complementary MOS transistors is constituted using a second poly Si layer as its gate electrode and using an impurity diffused layer formed in a first poly Si layer as its source and drain regions.

CONSTITUTION: In a complementary semiconductor integrated circuit for forming P-channel and N-channel MOS transistors on a one conductivity type semiconductor substrate (P-type Si substrate) 1, a first polycrystalline Si layer 4 is formed on the above substrate 1, while maintaining insulation, and a second polycrystalline Si layer 6 is formed on part of the layer 4 while maintaining insulation. A MOS transistor the other channel, which uses the layer 4 as its gate electrode and uses an impurity diffused layer of the other conductivity type formed in the substrate 1 as its source and drain regions, is formed. Moreover, the one-channel MOS transistor, which uses the layer 6 as its gate electrode and uses a one conductivity type impurity diffused layer formed in the layer 4 as its source and drain regions, is formed.