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Patent Searching and Data


Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS6394174
Kind Code:
A
Abstract:

PURPOSE: To prevent a test circuit from deteriorating and to test the function of a circuit to be tested at the time of packaging by fixing the source voltage of a testing circuit almost at 0V in its stand-by mode, and raising the source voltage above 3V only when the function is tested.

CONSTITUTION: A circuit block 104 is formed on a chip 101 and further a testing circuit block 102 and a power source control block 103 are formed. Then when a block 104 is in operation, the block 103 lowers the source voltage of the block 102 to 0V to suppress an increase in the threshold voltage shift of the MOSFET element in the block 104. On the other hand, when the block 104 is tested, the source voltage of the block 102 is raised above 3V by the block 103 and a test pattern generator included in the block 102 generates a pattern, which is inputted to the block 104. This result is returned to the block 102 and an internal data compressing circuit tests the block 104. Thus, the deterioration of the block 102 is suppressed and a normal function test is attained.


Inventors:
KATO MASATAKA
OKABE TAKEAKI
YAMAGUCHI NOBORU
Application Number:
JP23900386A
Publication Date:
April 25, 1988
Filing Date:
October 09, 1986
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G01R31/28; H01L21/822; H01L27/04; H01L21/66; (IPC1-7): G01R31/28; H01L21/66; H01L27/04
Domestic Patent References:
JPS5223736A1977-02-22
Attorney, Agent or Firm:
Katsuo Ogawa