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Patent Searching and Data


Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS6489000
Kind Code:
A
Abstract:

PURPOSE: To shorten a testing time while using a PROM writer on the market by supplying a specified logical value to a specified terminal from the outside and allowing the switching of the two modes of read/write at every word and read/write for plural words to be possible in a semiconductor IC incorporating a PROM.

CONSTITUTION: When the logical value zero is inputted to the PROM test mode terminal 1, the address of the PROM part is decided by the OR of an address most significant bit terminal 5 and a chip enable terminal 8. Therefore, when the terminal 8 takes the logical value 1, one of a low-order, and a high-order data input/output terminal 6 and 7 is made to be an active input/output port. When the logical value from the terminal is 1, a low-order and a high-order mat 2 and 3 are made to be an enable state and the terminals 6 and 7 go to active regardless of the value of the terminal 5 when a chip is selected by the terminal 8. Thus, the testing time is about 1/2 in comparison with the case that this mode is not used.


Inventors:
TANABE HIROKI
ISHIBASHI KENICHI
IWATA KATSUMI
ITO TAKASHI
Application Number:
JP24377087A
Publication Date:
April 03, 1989
Filing Date:
September 30, 1987
Export Citation:
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Assignee:
HITACHI LTD
HITACHI MICROCUMPUTER ENG
International Classes:
G11C17/00; G11C29/00; G11C29/02; (IPC1-7): G11C17/00; G11C29/00
Attorney, Agent or Firm:
Katsuo Ogawa (1 person outside)