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Patent Searching and Data


Title:
SEMICONDUCTOR INTEGRATED DEVICE
Document Type and Number:
Japanese Patent JPS61220450
Kind Code:
A
Abstract:

PURPOSE: To expand the range of an operating power source voltage, by imparting a reference voltage to a gate, imparting a power source voltage to a drain, imparting an operating voltage to an inner circuit from a source in NchFETs, and turning ON a PchFET, which detects the power source voltage and sends the power source voltage that is applied on the source to the inner circuit.

CONSTITUTION: NchFETs Q2 and Q3 are connected in series through the diodes and grounded, and a reference voltage 2Vth is formed. A power source voltage VCC is applied through a PchFET Q1, which is grounded through the gate and has a high resistance value. The voltage 2Vth is applied to the gate of NchFET Q4. The VCC is applied to the drain of the Q4. The VCC is sent to a ROM through the source. Before the VCC is decreased to the lower operating voltage limit VCC'+Vth(Q4) of the ROM, the voltage (chain line) divided by resistors R1 and R2 becomes lower than a logical threshold-value voltage VLT of an inverter IV. A Q5 is turned ON by the output of the IV. In the Q5, the VCC' becomes about the same value of the VCC without level loss such as seen in the Q4. Thus detection is performed before the operation of a constant voltage circuit becomes unstable, the VCC itself is supplied, and the range of the operating power source voltage is expanded.


Inventors:
FUJIKAWA TSUNEO
MATSUBARA KIYOSHI
Application Number:
JP6063985A
Publication Date:
September 30, 1986
Filing Date:
March 27, 1985
Export Citation:
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Assignee:
HITACHI MICROCUMPUTER ENG
HITACHI LTD
International Classes:
H01L27/04; G11C11/407; H01L21/822; H01L21/8246; H01L27/10; H01L27/112; (IPC1-7): H01L27/04; H01L27/10
Attorney, Agent or Firm:
Katsuo Ogawa