PURPOSE: To provide a semiconductor memory DMU realizing a high-speed access and a cache memory.
CONSTITUTION: In accordance with address decoder circuits DCRO-4 by which a first address signal is decoded and the selection signals of a memory cell is formed, cell arrays M0-M3 which are each provided corresponding to each address decoder, and the decoder output of a second address signal by which the cell array supplied and selected later from the first address signal is instructed, the selection of the output signal from an amplifier circuit or the selection of a write circuit WA in accordance with a write or read operation mode is carried out. Also, a latch function is added to the address decoder circuit, in which the selecting signal of the cell array corresponding by receiving the first address signal and decoding it is formed, a selection is made in accordance with the decoder output of the second address signal that is supplied later, and at the time of a write mode, the latch operation of the address decoder circuit is instructed to prolong its release to a adequate timing in the next cycle.
SHIRASAWA TAKAYUKI
SAKAGAMI YOSHIAKI
HITACHI HOKKAI SEMICONDUCTOR
HITACHI MICOM SYST KK