PURPOSE: To accelerate the access of a semiconductor memory so as to be available for the main storage of a processor without interposing a cache memory.

CONSTITUTION: This circuit is provided with a serial data register 2 storing the data by one row of a memory array 1 and a data input/output port 108 serially accessing to the serial data register 2 synchronizing with a clock 107. By a mask register 102, the data transfer by one row between the memory array 1 and the serial data register 2 is allowed at every bit. By the adoption of the serial access through the data input/output port 108, read and write related to a continuous address are accelerated.