To provide a semiconductor memory device in which power consumption in writing or reading is reduced.
A semiconductor memory device comprises: bit line pairs BLP0 to BLP7; word lines WL0 to WL3; and memory cells MC that are connected between a first bit line and second bit line of each of the bit line pairs. A switching section CSW1 selectively connects either a first bit line pair group of BLP1, BLP3, BLP5, and BLP7 or a second bit line pair group of BLP0, BLP2, BLP4, and BLP6 to a plurality of data lines LDQ1. In a data-reading operation or data-writing operation, the switching section executes both of the following during one activation period in which word lines selected out of the plurality of word lines are activated: a first switching operation for connecting the first bit line pair group to the plurality of data lines; and a second switching operation for connecting the second bit line pair group to the plurality of data lines.
INABA TSUNEO
Yasukazu Sato
Yasushi Kawasaki
Takeshi Sekine
Akaoka Akira