SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR TESTING THE SAME

Japanese Patent JP3956111

B2

PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which malfunction never be caused and operation can be performed with low power consumption by performing a test again and detecting optimum operation conditions for a cell being easy to be defect out of cells passing a test, and a method for testing the same.
SOLUTION: This device is provided with a memory cell array provided with memory cells decided as defect and repaired as a consequence of a first test and test cells decided as memory cells being easy to be defect most out of memory cells decided as passing the test and repaired, a test means by which a second test is performed with operation conditions previously set for the test cell, the operation conditions are adjusted for the test cell in accordance with a result of the second test, the second test is performed repeatedly, or the operation conditions adjusted finally are outputted, and a driving means for driving the memory cell array with operation conditions outputted from the test means.

Hong Xiang
Kim Hiroshi

JP2002141266A

August 08, 2007

May 16, 2002

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HYNIX SEMICONDUCTOR INC.

G01R31/28; G11C11/401; G11C29/56; G11C29/00; G11C29/08; G11C29/14; G11C29/44; G11C29/50; (IPC1-7): G11C29/00; G01R31/28; G11C11/401

JP2002157898A
JP3242895A
JP63291475A
JP10178108A
JP6284491A
JP63121196A
JP10199260A
JP52896A
JP11120800A
JP2000036200A
JP2000132996A
JP11066845A
JP11086598A
JP65075A
JP4252490A

Eiji Saegusa
Kakehi Yuro
Takeshi Ohara
Hiroji Nakagawa
Yasumitsu Tate
Kenji Saito
Jun Fujii
Hitoshi Seki
Mutsuko Nakano
Shinichi Mashita
Ryuji Inuchi

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