To avoid application of unnecessary high-voltage stress to circuit sections other than a dielectric layer between electrodes of a memory capacitor of a DRAM, at high-voltage test.

This semiconductor memory device has a memory cell comprised of a MOS transistor TN1 and a memory capacitor Cs, which is provided with a memory node potential setting means for setting a memory node MEM, a connecting node on one side of the source electrodes and the memory capacitor of the MOS transistor and a bit line BL to the same potential, and a memory cell plate potential setting means for setting a memory cell plate on the other side of electrodes of the memory capacitor to an arbitrary potential higher than that of the potential of the bit line BL and the memory node. For testing the semiconductor memory device, similar potential setting is performed for similar memory cells.