Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JP2000101039
Kind Code:
A
Abstract:
To provide a PROM, a DRAM and a ferroelectric memory equipped with highly reliable and highly integrated hierarchical bit lines that can increase the information read signal voltage.
In this memory device, the height of the main bit lines MB0, MB1, MB2 is made a half or less of the height of backing low resistance word lines Z0, Zm, X1, Xn. The main bit lines are formed in a layer with low wiring height other than the layer of power lines, ground lines and backing low resistance word lines, desirably in the top layer by using copper or tungsten as a main element.
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Inventors:
TAKEUCHI MIKI
TANIGUCHI YASUHIRO
YADORI SHOJI
HIRAKI MITSURU
TANAKA TOSHIHIRO
TANIGUCHI YASUHIRO
YADORI SHOJI
HIRAKI MITSURU
TANAKA TOSHIHIRO
Application Number:
JP26428398A
Publication Date:
April 07, 2000
Filing Date:
September 18, 1998
Export Citation:
Assignee:
HITACHI LTD
International Classes:
G11C11/41; G11C11/401; H01L21/8242; H01L27/108; (IPC1-7): H01L27/108; H01L21/8242; G11C11/41; G11C11/401
Attorney, Agent or Firm:
Ogawa Katsuo
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