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Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JP2013122985
Kind Code:
A
Abstract:

To suppress variation in characteristics between memory cells.

A memory cell array is configured to arrange memory cells having a variable resistive element at intersection points between a plurality of first wiring lines and a plurality of second wiring lines that are formed so as to cross each other. A control circuit selectively drives the first wiring lines and the second wiring lines. The variable resistive element is composed of a transition metal oxide film. An electrode connected to the variable resistive element includes a polysilicon electrode composed of polysilicon. A block layer is formed between the polysilicon electrode and the variable resistive element.


Inventors:
NOJIRI YASUHIRO
FUKUMIZU HIROYUKI
SEKINE KATSUYUKI
ISHIBASHI YUTAKA
Application Number:
JP2011270917A
Publication Date:
June 20, 2013
Filing Date:
December 12, 2011
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H01L27/105; G11C13/00; H01L27/10; H01L45/00; H01L49/00
Domestic Patent References:
JP2012523711A2012-10-04
JP2010225850A2010-10-07
JP2008160004A2008-07-10
JP2004158481A2004-06-03
JP2013522911A2013-06-13
Foreign References:
WO2011115924A12011-09-22
WO2010118380A22010-10-14
Attorney, Agent or Firm:
Kisaragi International Patent Business Corporation



 
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