Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JP2016021590
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor memory device which effectively prevents characteristic deterioration due to a pattern shift in gate formation while suppressing increase in cell area, and reduces resistance in a power voltage supply line.SOLUTION: In a semiconductor memory device, each memory cell includes two inverters respectively composed of first conductivity type driving transistors Qn1 and Qn2 and second conductivity type load transistors Qp1 and Qp2 which are electrically connected in series between a first power voltage supply line VDD and a second power voltage supply line VSS and of which gates are connected in common, and cross-connecting input and output. At least one of the first power voltage supply line VSS and the second power voltage supply line VSS is composed of groove wiring formed by filling inside of a through groove in an inter-layer insulating layer with conductive material.SELECTED DRAWING: Figure 14
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Inventors:
ISHIDA MINORU
Application Number:
JP2015188669A
Publication Date:
February 04, 2016
Filing Date:
September 25, 2015
Export Citation:
Assignee:
SONY CORP
International Classes:
H01L21/8244; H01L21/3205; H01L21/768; H01L23/522; H01L27/11
Domestic Patent References:
| JPH1056078A | 1998-02-24 | |||
| JPH09172078A | 1997-06-30 | |||
| JPH0817944A | 1996-01-19 | |||
| JPH04257258A | 1992-09-11 | |||
| JPH08288407A | 1996-11-01 | |||
| JPH04145656A | 1992-05-19 | |||
| JPH07161839A | 1995-06-23 | |||
| JPH08139092A | 1996-05-31 | |||
| JPH06104420A | 1994-04-15 |
Attorney, Agent or Firm:
Sadao Kumakura
Hiroshi Uesugi
Nobuyuki Taniguchi
Hiroshi Uesugi
Nobuyuki Taniguchi
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