Title:
半導体メモリ装置
Document Type and Number:
Japanese Patent JP4122248
Kind Code:
B2
Abstract:
A multi-level semiconductor memory device preferably includes a plurality of wordlines connected to memory cells configured to store multi-level data. A first circuit supplies a temperature-responsive voltage to a selected wordline in order to read a state of a selected memory cell. A second circuit supplies a predetermined voltage to non-selected wordlines. The first circuit preferably includes a semiconductor element that varies its resistance in accordance with temperature. Reliable program-verifying and reading functions are preferably provided despite migration of threshold voltage distribution profiles due to temperature variations.
Inventors:
Zhaodai He
Lee Yong-ta
Lee Yong-ta
Application Number:
JP2003086304A
Publication Date:
July 23, 2008
Filing Date:
March 26, 2003
Export Citation:
Assignee:
SAMSUNG ELECTRONICS CO.,LTD.
International Classes:
G11C16/06; G11C8/08; G11C11/56; G11C16/02; G11C16/04
Domestic Patent References:
| JP2001035177A | ||||
| JP7066680A | ||||
| JP10027026A | ||||
| JP8171795A | ||||
| JP10320983A | ||||
| JP7183559A |
Attorney, Agent or Firm:
Makoto Hagiwara