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Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JPH01179292
Kind Code:
A
Abstract:

PURPOSE: To remarkably reduce current consumption by separating a digit line arranged in a row direction or a column direction to be connected to a selected a storage cell to two or more pairs of groups, and enabling access to each group independently.

CONSTITUTION: A write operation is executed by setting a word line W121 and a digit selection line Y121 at high levels, and setting one side of a pair of digit lines D113 and D114 at the high level and the other side at a low level based on whether write information is set at 0 or 1. Meanwhile, a readout operation is executed in such a way that the word line W121 and the digit selection line Y121 are set at the high levels similarly as the write operation, and the information of a storage cell circuit E11 is taken out at the pair of digit lines D113 and D114 and at data lines D130 and D140 after passing digit signal transmission gates Q113 and Q114, and decision for 0 or 1 is performed. Thus, the digit line connected to the cell circuit E11 is provided with an E21 only as a storage cell load, and the potential of the digit lines D213 and D214 of storage cell circuits E31 and E41 remain unchanged.


Inventors:
YASUOKA NOBUYUKI
Application Number:
JP33229387A
Publication Date:
July 17, 1989
Filing Date:
December 29, 1987
Export Citation:
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Assignee:
NEC CORP
International Classes:
G11C11/41; G11C11/34; (IPC1-7): G11C11/34
Domestic Patent References:
JPS5766587A1982-04-22
JPS5994296A1984-05-30
JPS6111991A1986-01-20
JPS6299982A1987-05-09
Attorney, Agent or Firm:
Takashi Koshiba



 
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