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Patent Searching and Data


Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JPH023144
Kind Code:
A
Abstract:

PURPOSE: To execute high speed transmitting by forming a transfer gate to be in a conductive condition when a comparing data signal is a first level and to transfer read data and an inverter to be in an active condition when it is a second level and to invert the read data.

CONSTITUTION: When a comparing data signal 1 connected between a reading data bus 2 and a comparing data bus 4 is a grounding electric potential level '0', data RD of the bus 2 pass through only a transfer gate 31 and are transferred to the comparing data bus 4 as they are. Besides, when the signal 1 is a source potential level '1', the data RD are inverted and transferred to the comparing data bus 4 through only an inverter circuit 32. That is, when the data transferred to the comparing data bus 4 are CD, the relation of the comparing data signal 1, the data RD and CD becomes like a truth figure, an exclusive OR operating function is performed and a passing gate circuit is satisfied with one stage, and the transferring time of the data can be shortened.


Inventors:
MAESAKO ISATO
Application Number:
JP14881088A
Publication Date:
January 08, 1990
Filing Date:
June 15, 1988
Export Citation:
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Assignee:
NIPPON ELECTRIC IC MICROCOMPUT
International Classes:
G11C11/409; G11C11/34; G11C11/401; (IPC1-7): G11C11/34; G11C11/401
Domestic Patent References:
JPS6214523A1987-01-23
JPS5982695A1984-05-12
JPS59207477A1984-11-24
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)