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Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JPH03123074
Kind Code:
A
Abstract:

PURPOSE: To enhance a cell in capacity keeping it small in area by a method wherein a cell plate is formed so as to cover the upside and the underside of a storage node.

CONSTITUTION: The surface of a substrate 1 is element-isolated by a field isolation insulating film 2, a interlaminar insulating film 4 is formed on a transfer gate 3, and then a cell plate material 5 is formed, which is formed into a first cell plate 5 through an etching treatment. Then, a contact hole 14 is formed. In succession, a gate oxide film 7 is formed on the first cell plate 5 as a first capacitor insulating film, and a storage node material is deposited, which is patterned into a storage node 8. Next, an oxidation process is carried out to form a gate oxide film 71 on the surface of storage node 8 as a second capacitor insulating film, a second cell plate material is deposited, which is patterned into a second cell plate 9, and then a stacked capacitor cell provided with the first and the second cell plate, 5 and 9, is formed on the upside and the underside of the storage anode 8 respectively.


Inventors:
MAMETANI TOMOHARU
Application Number:
JP26081289A
Publication Date:
May 24, 1991
Filing Date:
October 04, 1989
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L27/04; H01L21/822; H01L21/8242; H01L27/10; H01L27/108; (IPC1-7): H01L27/04; H01L27/108
Attorney, Agent or Firm:
Masuo Oiwa (2 outside)



 
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